Methods of fabricating three-dimensional capacitor structures having planar metal-insulator-metal and vertical capacitors therein
US7879681B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 6, 2008 |
| Grant date | Feb 1, 2011 |
| Priority date | — |
| Expiry date | Oct 6, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of forming a three-dimensional capacitor network may include forming a first horizontal MIM capacitor on a semiconductor substrate and forming a first interlayer insulating layer on the first horizontal MIM capacitor. A first vertical capacitor electrode is then formed in the first interlayer insulating layer and a second horizontal MIM capacitor is formed on the first interlayer insulating layer. This second horizontal MIM capacitor may be formed by forming an upper capacitor electrode and a lower capacitor electrode. The upper capacitor electrode may be electrically connected by the first vertical capacitor electrode to an upper capacitor electrode of the underlying first MIM capacitor. The lower capacitor electrode, which may be formed in the first interlayer insulating layer, may extend opposite the upper electrodes of the first and second MIM capacitors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.