Memory and manufacturing method thereof
US7879706B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2007 |
| Grant date | Feb 1, 2011 |
| Priority date | — |
| Expiry date | Nov 5, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/037
Abstract
A memory having isolated dual memory cells is provided. A first isolation wall and a second isolation wall are separately disposed between a source and a drain on a substrate. An isolation bottom layer and a polysilicon layer are orderly disposed on the substrate between the first and the second isolation walls. A first charge storage structure and a first gate are orderly disposed on the substrate between the first isolation wall and the source. A second charge storage structure and a second gate are orderly disposed on the substrate between the second isolation wall and the drain. A word line disposed on the polysilicon layer, the first gate, the second gate, the first isolation wall and the second isolation wall is electrically connected to the first gate, the second gate and the polysilicon layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.