NAND flash memory device having dummy memory cells and methods of operating same
US7881114B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 19, 2008 |
| Grant date | Feb 1, 2011 |
| Priority date | — |
| Expiry date | Dec 19, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3445
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A NAND flash memory device includes a control circuit configured to apply, during a program operation, a first word line voltage to non-selected ones of a plurality of serially-connected memory cells, a second word line voltage greater than the first word line voltage to a selected one of the plurality of memory cells, and a third word line voltage lower than the first word line voltage to a dummy memory cell connected in series with the plurality of memory cells. In other embodiments, a control circuit is configured to program a dummy memory cell before and/or after each erase operation on a plurality of memory cells connected in series therewith. In still other embodiments, a control circuit is configured to forego erasure of a dummy memory cell while erasing a plurality of memory cells connected in series therewith.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.