Read assist for memory circuits with different precharge voltage levels for bit line pair
US7881137B2 · kind B2 · utility
19Cited by
6References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 23, 2008 |
| Grant date | Feb 1, 2011 |
| Priority date | — |
| Expiry date | Apr 18, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/417
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method increases stability of a memory circuit by pre-charging at least one bit line of the memory circuit to a first voltage, pre-charging at least one other bit line of the memory circuit to a second voltage, and equalizing charge across the bit lines so that the bit lines are pre-charged with a third voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.