Command packet packing to mitigate CRC overhead
US7881303B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 13, 2006 |
| Grant date | Feb 1, 2011 |
| Priority date | — |
| Expiry date | Feb 10, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/18
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
In an embodiment, a node comprises a packet scheduler configured to schedule packets to be transmitted on a link and an interface circuit coupled to the packet scheduler and configured to transmit the packets on the link. The interface circuit is configured to generate error detection data covering the packets, wherein the error detection data is transmitted between packets on the link. The interface circuit is configured to cover up to N packets with one transmission of error detection data, where N is an integer >=2. The number of packets covered with one transmission of error detection data is determined by the interface circuit dependent on an availability of packets to transmit. In another embodiment, the interface circuit is configured to dynamically vary a frequency of transmission of the error detection data on the link based on an amount of bandwidth being consumed on the link.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.