Method and system for implementing prioritized refresh of DRAM based cache
US7882302B2 · kind B2 · utility
1Cited by
18References
20Claims
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Key dates
| Filing date | Dec 4, 2007 |
| Grant date | Feb 1, 2011 |
| Priority date | — |
| Expiry date | Sep 18, 2029 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for implementing prioritized refresh of a multiple way, set associative DRAM based cache includes identifying, for each of a plurality of sets of the cache, the existence of a most recently used way that has not been accessed during a current assessment period; and for each set, refreshing only the identified most recently used way of the set not accessed during the current assessment period, while ignoring the remaining ways of the set; wherein a complete examination of each set for most recently used ways therein during the current assessment period constitutes a sweep of the cache.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.