Primitives to enhance thread-level speculation
US7882339B2 · kind B2 · utility
51Cited by
5References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 23, 2005 |
| Grant date | Feb 1, 2011 |
| Priority date | — |
| Expiry date | Apr 22, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3861
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor may include an address monitor table and an atomic update table to support speculative threading. The processor may also include one or more registers to maintain state associated with execution of speculative threads. The processor may support one or more of the following primitives: an instruction to write to a register of the state, an instruction to trigger the committing of buffered memory updates, an instruction to read the a status register of the state, and/or an instruction to clear one of the state bits associated with trap/exception/interrupt handling. Other embodiments are also described and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.