Bryant Bigbee
47Patents
11h-index
88Co-inventors
78Inventor score
Filing activity: Aug 18, 1997 → Sep 14, 2020
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6349380B1 | Linear address extension and mapping to physical memory using 4 and 8 byte page table entries in a 32-bit microprocessor | Physics | 75 | Expired |
| US7882339B2 | Primitives to enhance thread-level speculation | Physics | 51 | Expired |
| US8762694B1 | Programmable event-driven yield mechanism | Physics | 16 | Expired |
| US7810083B2 | Mechanism to emulate user-level multithreading on an OS-sequestered sequencer | Physics | 15 | Active |
| US7974416B2 | Providing a secure execution mode in a pre-boot environment | Physics | 15 | Expired |
| US6920581B2 | Method and apparatus for functional redundancy check mode recovery | Physics | 13 | Expired |
| US8010969B2 | Mechanism for monitoring instruction set based thread execution on a plurality of instruction sequencers | Physics | 13 | Active |
| US7743233B2 | Sequencer address management | Physics | 13 | Active |
| US7849465B2 | Programmable event driven yield mechanism which may activate service threads | Physics | 12 | Active |
| US10162694B2 | Hardware apparatuses and methods for memory corruption detection | Physics | 11 | Active |
| US6289431A | Method and apparatus for accessing more than 4 Gigabytes of physical memory with 4-byte table entries | Physics | 11 | Expired |
| US8301868B2 | System to profile and optimize user software in a managed run-time environment | Physics | 11 | Expired |
| US9990206B2 | Mechanism for instruction set based thread execution of a plurality of instruction sequencers | Physics | 9 | Active |
| US8516483B2 | Transparent support for operating system services for a sequestered sequencer | Physics | 8 | Active |
| US5946713A | Memory attribute palette | Physics | 7 | Expired |
| US8479217B2 | Apparatus, system, and method for persistent user-level thread | Physics | 5 | Active |
| US8171268B2 | Technique for context state management to reduce save and restore operations between a memory and a processor using in-use vectors | Physics | 5 | Active |
| US6526431B1 | Maintaining extended and traditional states of a processing unit in task switching | Physics | 5 | Expired |
| US8719819B2 | Mechanism for instruction set based thread execution on a plurality of instruction sequencers | Physics | 4 | Active |
| US7793111B1 | Mechanism to handle events in a machine with isolated execution | Physics | 4 | Expired |
| US9026773B2 | Providing a secure execution mode in a pre-boot environment | Physics | 3 | Active |
| US6857066B2 | Apparatus and method to identify the maximum operating frequency of a processor | Physics | 3 | Expired |
| US8914618B2 | Instruction set architecture-based inter-sequencer communications with a heterogeneous resource | Physics | 2 | Active |
| US8607235B2 | Mechanism to schedule threads on OS-sequestered sequencers without operating system intervention | Physics | 2 | Active |
| US10275598B2 | Providing a secure execution mode in a pre-boot environment | Physics | 2 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.