Reducing inefficiencies of multi-clock-domain interfaces using a modified latch bank
US7882385B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 5, 2007 |
| Grant date | Feb 1, 2011 |
| Priority date | — |
| Expiry date | Sep 19, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0045
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A system and method for improving the performance and efficiency of multi-clock-domain data transmission interfaces. The data transmission interface may include a modified slave latch which includes one or more clock splitters and one or more transmission gates may be used. By having such a configuration, space requirements are reduced and a reduction of the number of devices necessary for a multi-domain interface may be realized. The configuration may further allow for independent cycle stealing of N:1 and N:2 logical paths, thus allowing for timing resolution solutions that use fewer devices versus implementations that require the tuning of each individual bit in the cross-clock-domain interface. By implementing such a data transmission interface, space and power requirements may be reduced and timing criticalities may be more easily managed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.