Timing and signal integrity analysis of integrated circuits with semiconductor process variations
US7882471B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 15, 2006 |
| Grant date | Feb 1, 2011 |
| Priority date | — |
| Expiry date | May 28, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/367
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment of the invention, a method of statically analyzing an integrated circuit with process and environment variations is provided. The method includes characterizing each circuit cell of a cell library for a sensitivity to process parameter variations within a predetermined range; creating a timing graph corresponding to a netlist representing an integrated circuit design; along nodes of the timing graph, computing delay values including sensitivities to process variations; for each selected output node of the netlist, propagating a full timing value function with the sensitivities to the selected output nodes; and generating a parameterized timing report including the sensitivities to the process variations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.