Method for checking constraints equivalence of an integrated circuit design
US7882483B2 · kind B2 · utility
3Cited by
3References
28Claims
0Family size
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Key dates
| Filing date | May 31, 2007 |
| Grant date | Feb 1, 2011 |
| Priority date | — |
| Expiry date | Aug 1, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The equivalence of two or more constraint files of an integrated circuit (IC) design are checked. The comparison is performed between files at the same stage of design, files that correspond to different stages of the design flow, or between top-level and block-level constraint files.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.