Method and structure for reducing induced mechanical stresses

US7883948B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Brian J. Greene · Wappingers Falls, US
• Rajesh Rengarajan · Fishkill, US

Key dates

• Filing date: May 14, 2009
• Grant date: Feb 8, 2011
• Expiry date: May 14, 2029

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/015

Abstract

Methods and structures for relieving stresses in stressed semiconductor liners. A stress liner that enhances performance of either an NFET or a PFET is deposited over a semiconductor to cover the NFET and PFET. A disposable layer is deposited to entirely cover the stress liner, NFET and PFET. This disposable layer is selectively recessed to expose only the single stress liner over a gate of the NFET or PFET that is not enhanced by such stress liner, and then this exposed liner is removed to expose a top of such gate. Remaining portions of the disposable layer are removed, thereby enhancing performance of either the NFET or PFET, while avoiding degradation of the NFET or PFET not enhanced by the stress liner. The single stress liner is a tensile stress liner for enhancing performance of the NFET, or it is a compressive stress liner for enhancing performance of the PFET.