Advanced CMOS using super steep retrograde wells
US7883977B2 · kind B2 · utility
121Cited by
9References
4Claims
0Family size
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Key dates
| Filing date | Jan 20, 2009 |
| Grant date | Feb 8, 2011 |
| Priority date | — |
| Expiry date | Jan 20, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/60
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer (110) beneath the gate dielectric (50) and source and drain regions (80) of a MOS transistor. The carbon containing layer (110) will prevent the diffusion of dopants into the region (40) directly beneath the gate dielectric layer (50).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.