Method for manufacturing simox wafer
US7884000B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 3, 2007 |
| Grant date | Feb 8, 2011 |
| Priority date | — |
| Expiry date | Sep 22, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/26533
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing SIMOX wafer, wherein roughness (Rms) of an SOI layer and roughness (Rms) of an interface between the SOI layer and a BOX layer can be reduced. The method includes forming a first ion-implanted layer containing highly concentrated oxygen within a wafer; forming a second ion-implanted amorphous layer; and a high temperature heat treatment, transforming the first and second ion-implanted layers into a BOX layer by holding the wafer at a temperature between 1300° C. or more and a temperature less than a silicon melting point in an atmosphere containing oxygen, wherein when a first dose amount in forming the first ion-implanted layer is set to 2×1017 to 3×1017 atoms/cm2, the first implantation energy set to 165 to 240 keV and a second dose amount in forming the second ion-implanted layer is set to 1x1014 to 1x1016 atoms/cm2.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.