Maskless process for suspending and thinning nanowires
US7884004B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 4, 2009 |
| Grant date | Feb 8, 2011 |
| Priority date | — |
| Expiry date | Feb 4, 2029 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S977/762
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Semiconductor-based electronic devices and techniques for fabrication thereof are provided. In one aspect, a device is provided comprising a first pad; a second pad and a plurality of nanowires connecting the first pad and the second pad in a ladder-like configuration formed in a silicon-on-insulator (SOI) layer over a buried oxide (BOX) layer, the nanowires having one or more dimensions defined by a re-distribution of silicon from the nanowires to the pads. The device can comprise a field-effect transistor (FET) having a gate surrounding the nanowires wherein portions of the nanowires surrounded by the gate form channels of the FET, the first pad and portions of the nanowires extending out from the gate adjacent to the first pad form a source region of the FET and the second pad and portions of the nanowires extending out from the gate adjacent to the second pad form a drain region of the FET.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.