Decoupling capacitor, wafer stack package including the decoupling capacitor, and method of fabricating the wafer stack package
US7884458B2 · kind B2 · utility
4Cited by
1References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 6, 2007 |
| Grant date | Feb 8, 2011 |
| Priority date | — |
| Expiry date | Nov 3, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A decoupling capacitor, a wafer stack package including the decoupling capacitor, and a method of fabricating the wafer stack package are provided. The decoupling capacitor may include a first electrode formed on an upper surface of a first wafer, a second electrode formed on a lower surface of a second wafer, and an adhesive material having a high dielectric constant and combining the first wafer with the second wafer. In the decoupling capacitor the first and second electrodes operate as two electrodes of the decoupling capacitor, and the adhesive material operates as a dielectric of the decoupling capacitor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.