HDL design structure for integrating test structures into an integrated circuit design
US7884599B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 21, 2008 |
| Grant date | Feb 8, 2011 |
| Priority date | — |
| Expiry date | Apr 23, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318511
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A hardware description language (HDL) design structure for performing device-specific testing and acquiring parametric data on integrated circuits, such that each chip can be tested individually without excessive test time requirements, additional silicon, or special test equipment. The HDL design structure includes a functional representation of at least one device test structure integrated into an IC design which tests a set of dummy devices that are identical or nearly identical to a selected set of devices contained in the IC. The test structures are integrated from a device under test (DUT) library according to customer requirements and design requirements. The functional representations of selected test structures are further prioritized and assigned to design elements within the design in order of priority. Placement algorithms use design, layout, and manufacturing requirements to place the selected functional representations of test structures into the final layout of the design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.