PLD providing soft wakeup logic
US7884640B2 · kind B2 · utility
7Cited by
5References
27Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 19, 2008 |
| Grant date | Feb 8, 2011 |
| Priority date | — |
| Expiry date | Dec 19, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17784
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A programmable logic device (PLD) with a plurality of programmable regions is disclosed. Some of the programmable regions have switch power or ground supplies to allow them to be put into a low-power state in one or more low-power modes. At least one of the programmable regions always remains on during the low-power modes to enable the user to design custom PLD power management logic that may be placed in the always-on programmable region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.