No stress level shifter
US7884646B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 24, 2009 |
| Grant date | Feb 8, 2011 |
| Priority date | — |
| Expiry date | Feb 24, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00315
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A voltage level shifting circuit may include a differential first-stage level shifter that receives a binary input signal and generates a non-inverted first-stage shifted output signal and an inverted first-stage shifted output signal, a second-stage level shifter that receives the first-stage shifted output signals and generates a non-inverted second-stage shifted output signal and an inverted second-stage shifted output signal, and a signal generator that generates a level shifted final output signal corresponding to the binary input signal that is based on the non-inverted second-stage shifted output signal and the inverted second-stage shifted output signal. The voltage swing of the first stage output signals may be limited to swing between a non-zero lower value and an upper value that is less than or equal to a source-to-drain voltage rating of transistors in the differential first-stage level shifter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.