Analog comparator comprising a digital offset compensation
US7884650B2 · kind B2 · utility
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6References
23Claims
0Family size
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Key dates
| Filing date | Nov 14, 2008 |
| Grant date | Feb 8, 2011 |
| Priority date | — |
| Expiry date | Mar 4, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45726
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A digital compensation of an input stage of a comparator may be achieved by providing switched load elements, which may be appropriately connected to the differential input pair of the comparator in order to match transistor characteristics of the input pair and also match the load value of the input stage. Thus, enhanced offset behavior may be accomplished without providing an external signal and/or without requiring complex reference voltages/currents.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.