Method for low-stress multilevel reading of phase change memory cells and multilevel phase change memory
US7885101B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 29, 2008 |
| Grant date | Feb 8, 2011 |
| Priority date | — |
| Expiry date | Jul 15, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2013/0076
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to a method for multilevel reading of a phase change memory cell a bit line (9) and a PCM cell (2) are first selected and a first bias voltage (VBL, V00) is applied to the selected bit line (9). A first read current (IRD00), that flows through the selected bit line (9) in response to the first bias voltage (VBL, V00), is compared with a first reference current (I00). The first reference current (I00) is such that the first read current (IRD00) is lower than the first reference current (I00), when the selected PCM cell (2) is in a reset state, and is otherwise greater. It is then determined whether the selected PCM cell (2) is in the reset state, based on comparing the first read current (IRD00) with the first reference current (I00). A second bias voltage (VBL, V01), greater than the first bias voltage (VBL, V00), is applied to the selected bit line (9) if the selected PCM cell (2) is not in the reset state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.