Three dimensional twisted bitline architecture for multi-port memory
US7885138B2 · kind B2 · utility
5Cited by
10References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 19, 2007 |
| Grant date | Feb 8, 2011 |
| Priority date | — |
| Expiry date | Jul 29, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/412
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present invention provide a memory array of dual part cells and design structure thereof. The memory array has a pair of twisted write bit lines and a pair of twisted read bit lines for each column. The twist is made by alternating the vertical position of each bit line pair in each section of a column, with the result of generating common mode nose and of reducing differential mode noise.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.