Patent · US Active

Modeling asynchronous behavior from primary inputs and latches

US7885801B2 · kind B2 · utility

1Cited by

33References

12Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Zoltan T. Hidvegi · Round Rock, US
Yee Ja · Round Rock, US
Bradley Nelson · Austin, US

Key dates

Filing date	Jul 7, 2008
Grant date	Feb 8, 2011
Priority date	—
Expiry date	Jun 28, 2029

Classification

Technology area (CPC G)Physics
CPC primaryG06F30/33
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Asynchronous behavior of a circuit is emulated by modifying a netlist to insert additional logic at a driving element such as a latch. The additional logic outputs one of (i) a present output from the driving element, (ii) a delayed output from the driving element, or (iii) a random value, which drives downstream logic. The output of the additional logic is selectively responsive to a user-controlled skew enable input. The invention allows for simpler data skew logic transformations which are applicable to both latches and primary inputs, with no dependencies on any clock net.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.