Patent · US Active

Integrated circuit testing using segmented scan chains

US7886207B1 · kind B1 · utility

1Cited by
18References
20Claims
0Family size

Assignee

Inventor

Key dates

Filing dateMay 22, 2009
Grant dateFeb 8, 2011
Priority date—
Expiry dateMay 22, 2029

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG01R31/31855
  • WIPO fieldMeasurement
  • WIPO sectorInstruments

Abstract

An integrated circuit includes a plurality of logic circuits and a scan chain for testing the plurality of logic circuits. The plurality of logic circuits include the first and second logic circuits. The scan chain includes the first and second scan chain portions. The first scan chain portion is configured to test the first logic circuit based on a scan input test pattern applied thereto and output the first output test pattern. The second scan chain portion is configured to test the second logic circuit based on the first output test pattern and output the second output test pattern. A switching unit is provided to select and output one of the first output test pattern and the second output test pattern as a scan output test.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.