Method of manufacturing capacitor-embedded PCB
US7886414B2 · kind B2 · utility
5Cited by
9References
5Claims
0Family size
Assignee
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Key dates
| Filing date | Apr 22, 2008 |
| Grant date | Feb 15, 2011 |
| Priority date | — |
| Expiry date | Jul 29, 2028 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49167
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a capacitor-embedded PCB is disclosed. The method may include fabricating a capacitor substrate having at least one inner electrode formed on one side of a dielectric layer; aligning a semi-cured insulation layer with one side of a core layer, and aligning the capacitor substrate with the semi-cured insulation layer such that the inner electrode faces the semi-cured insulation layer; and collectively stacking the core layer, the semi-cured insulation layer, and the capacitor substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.