Method of fabricating a high performance power MOS
US7888216B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 9, 2010 |
| Grant date | Feb 15, 2011 |
| Priority date | — |
| Expiry date | Apr 9, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/157
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a semiconductor device includes forming in the substrate a well region comprising a first type of dopant; forming in the well region a base region comprising a second type of dopant different from the first type of dopant; and forming in the substrate source and drain regions comprising the first type of dopant. The method further includes forming on the substrate a gate electrode interposed laterally between the source and drain regions; and forming on the substrate a gate spacer disposed laterally between the source region and the gate electrode adjacent a side of the gate electrode and having a conductive feature embedded therein. The well region surrounds the drain region and the base region, and the base region is disposed partially underlying the gate electrode surrounding the source region defining a channel under the gate electrode of having a length substantially less than half the length of the gate electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.