On-chip bias voltage temperature coefficient self-calibration mechanism
US7889575B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 22, 2008 |
| Grant date | Feb 15, 2011 |
| Priority date | — |
| Expiry date | Jan 2, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2217/0018
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques and corresponding circuitry for deriving a supply a bias voltage for a memory cell array from a received reference voltage is presented. The circuit includes a voltage determination circuit, which is connected to receive the reference voltage and generate from it the bias voltage, a temperature sensing circuit, and a calibration circuit. The calibration circuit is connected to receive the bias voltage and to receive a temperature indication from the temperature sensing circuit and determine from the bias voltage and temperature indication a compensation factor that is supplied to the voltage determination circuit, which adjusts the bias voltage based upon the compensation factor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.