Processing unit incorporating L1 cache bypass
US7890699B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 10, 2008 |
| Grant date | Feb 15, 2011 |
| Priority date | — |
| Expiry date | May 3, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0811
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit arrangement and method bypass the storage of requested data in a higher level cache of a multi-level memory architecture during the return of the requested data to a requester, while caching the requested data in a lower level cache. For certain types of data, e.g., data that is only used once and/or that is rarely modified or written back to memory, bypassing storage in a higher level cache reduces the likelihood of the requested data casting out frequently used data from the higher level cache. By caching the data in a lower level cache, however, the lower level cache can still snoop data requests and return requested data in the event the data is already cached in the lower level cache.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.