Program memory test access collar
US7890804B2 · kind B2 · utility
8Cited by
4References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 28, 2007 |
| Grant date | Feb 15, 2011 |
| Priority date | — |
| Expiry date | Nov 11, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4243
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory access device includes logic to switch data from a processor memory bus to a memory bus in a first operational mode, and to switch data from a test bus to the memory bus in a second operational mode, and logic to switch address signals from the processor memory bus to the memory bus in the first operational mode. In the second operational mode the device accepts from the test bus a starting memory address for memory reads and writes, and automatically and independently of the test bus adjusts a memory address for reads and writes during burst memory operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.