Patent · US Active

Variable clocked scan test improvements

US7890899B2 · kind B2 · utility

22Cited by

7References

14Claims

0Family size

Assignee

Intellectual Ventures II LLC · US

Inventors

Laurence H. Cooke · Los Gatos, US
Bulent Dervisoglu · Mountain View, US

Key dates

Filing date	Mar 11, 2008
Grant date	Feb 15, 2011
Priority date	—
Expiry date	Apr 14, 2029

Classification

Technology area (CPC G)Physics
CPC primaryG01R31/318552
WIPO fieldMeasurement
WIPO sectorInstruments

Abstract

Addition of specific test logic may improve the level of test vector compression achieved from existing variable scan test logic. Methods for determining the compressed vectors' states, given the desired uncompressed vectors' values may be used, and techniques for selectively enabling test or other features on a chip by inserting the proper code or codes into the chip may further be used. Techniques may be used to incorporate and apply various types of reset operations to multiple strings of variable scan test logic, as may methods to minimize the test vector compression computation time.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.