Method and structure for SOI body contact FET with reduced parasitic capacitance
US7893494B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 18, 2008 |
| Grant date | Feb 22, 2011 |
| Priority date | — |
| Expiry date | Sep 4, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0212
Abstract
In one embodiment, the present invention provides a semiconductor device that includes a substrate including a semiconducting layer positioned overlying an insulating layer the semiconducting layer including a semiconducting body and isolation regions present about a perimeter of the semiconducting body; a gate structure overlying the semiconducting layer of the substrate, the gate structure present on a first portion on an upper surface of the semiconducting body; and a silicide body contact that is in direct physical contact with a second portion of the semiconducting body that is separated from the first portion of the semiconducting body by a non-silicide semiconducting region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.