Semiconductor package apparatus
US7893526B2 · kind B2 · utility
7Cited by
4References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 30, 2008 |
| Grant date | Feb 22, 2011 |
| Priority date | — |
| Expiry date | Mar 26, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package apparatus comprises: at least one semiconductor chip; and a circuit board on which the semiconductor chip is installed, wherein at least one conductive plane for improving power and/or ground characteristics is positioned on a side of the semiconductor chip. In this manner, fabrication cost for the semiconductor package apparatus can be mitigated, and power and/or ground characteristics can be improved so as to readily control impedance of signal lines. As a result, reliability of the operation of the semiconductor package apparatus can be improved, and noise and malfunction can be prevented.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.