Multiple-stage, signal edge alignment apparatus and methods
US7893741B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 12, 2009 |
| Grant date | Feb 22, 2011 |
| Priority date | — |
| Expiry date | Jun 12, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00234
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Signal edge alignment embodiments include multiple delay stages connected in series. Each delay stage includes a delay line, an interface circuit, and a tap selection circuit. The delay line applies fixed-width delays to an input signal to produce delayed versions of the input signal at a plurality of taps. The interface circuit, which is characterized by an inherent interface circuit delay, passes one of the delayed versions to an interface circuit output in response to a control signal. The tap selection circuit determines a finally-identified tap of the plurality of taps by determining an initially-identified tap at which a delayed version of the input signal most closely has a desired alignment with the input signal, and by identifying the finally-identified tap in the control signal as a tap that occurs earlier in the delay line than the initially-identified tap. This compensates for the inherent delay of the delay stage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.