Patent · US Active

Method and apparatus for reducing charge trapping in high-k dielectric material

US7894240B2 · kind B2 · utility

4Cited by

1References

29Claims

0Family size

Assignee

Qimonda AG · DE

Inventors

Michael Beck · Milpitas, US
Martin Kerber · Munich, DE
Peter Lahnor · Dresden, DE
Roland Thewes · Puchheim, DE

Key dates

Filing date	Aug 29, 2008
Grant date	Feb 22, 2011
Priority date	—
Expiry date	Aug 15, 2029

Classification

Technology area (CPC G)Physics
CPC primaryG11C2211/4068
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

In one embodiment, an integrated circuit includes a memory array having a plurality of capacitors for storing data of an initial state in the memory array in an initial state. The integrated circuit also includes circuitry for occasionally inverting the data stored by the plurality of capacitors and tracking whether the current state of the data stored by the plurality of capacitors corresponds to the initial state. The circuitry inverts the data read out of the memory array during a read operation when the current state of the data does not correspond to the initial state.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.