Thyristor based memory cell
US7894255B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 25, 2007 |
| Grant date | Feb 22, 2011 |
| Priority date | — |
| Expiry date | Jul 25, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D18/251
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A new memory cell contains only a single thyristor without the need to include an access transistor. A memory array containing these memory cells can be fabricated on bulk silicon wafer. Each memory cell is separated from other memory cells by shallow trench isolation regions. The memory cell comprises a thyristor body and a gate. The thyristor body has two end region and two base regions. The gate is positioned over and insulated from at least a portion of one base region and offset from another base region. A first end region is connected to one of a word line, a bit line and a third line. A second end region is connected to another of the word line, bit line, and third line. The gate is connected to the remaining of the word line, bit line and third line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.