Multi-rate simulation scheduler for synchronous digital circuits in a high level modeling system
US7895026B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 16, 2007 |
| Grant date | Feb 22, 2011 |
| Priority date | — |
| Expiry date | Dec 22, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/331
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer-implemented method of scheduling a multi-rate, synchronous circuit design for simulation within a high-level modeling system. The method can include determining a component clocking rate for each of a plurality of synchronous components of the circuit design and classifying each of the plurality of synchronous components into a plurality of schedules according to component clocking rate. For each clock cycle during simulation, the method can include selecting one of the plurality of schedules and executing each synchronous component of the selected schedule. A value determined through execution of a synchronous component of the circuit design can be output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.