Mechanism for using performance counters to identify reasons and delay times for instructions that are stalled during retirement
US7895421B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 12, 2007 |
| Grant date | Feb 22, 2011 |
| Priority date | — |
| Expiry date | May 29, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/885
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method of accounting for lost clock cycles in a microprocessor. A method includes detecting a first reason which prevents exit of an entry from an instruction retirement queue, and incrementing a first count corresponding to the first reason, wherein the first count is incremented while the first reason prevents exit of the entry from the queue. A first point in time is determined when said first reason no longer prevents exit of the entry from the queue. A second reason which prevents exit of the entry from the queue is detected, wherein the second reason came into existence prior to said first point in time. A second count corresponding to the second reason is incremented, wherein incrementing the second count begins at the first point in time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.