Packet queuing, scheduling and ordering
US7895431B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 6, 2004 |
| Grant date | Feb 22, 2011 |
| Priority date | — |
| Expiry date | May 2, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L63/166
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for ordering, synchronizing and scheduling work in a multi-core network services processor is provided. Each piece of work is identified by a tag that indicates how the work is to be synchronized and ordered. Throughput is increased by processing work having different tags in parallel on different processor cores. Packet processing can be broken up into different phases, each phase having a different tag dependent on ordering and synchronization constraints for the phase. A tag switch operation initiated by a core switches a tag dependent on the phase. A dedicated tag switch bus minimizes latency for the tag switch operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.