Integrated circuit using speculative execution
US7895469B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 14, 2008 |
| Grant date | Feb 22, 2011 |
| Priority date | — |
| Expiry date | Aug 15, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3869
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit 2 is provided with a plurality of pipeline stages 10. These pipeline stages 10 have speculative processing control circuitry 12 which permits speculative processing in downstream pipeline stages and triggers a first error recovery operation (partial pipeline flushing) if such speculative processing is determined to be based upon an error. The pipeline stage 10 further includes speculative error detecting circuitry 14 which generates a prediction nc regarding whether or not the processing circuitry 18 will produce an error. This prediction is used to trigger a second error recovery operation (partial pipeline stall). This second error recovery operation has a lower performance penalty than the first error recovery operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.