Verification method with the implementation of well voltage pseudo diodes
US7895554B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 21, 2007 |
| Grant date | Feb 22, 2011 |
| Priority date | — |
| Expiry date | Jan 10, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of verifying consistency between a circuit schematic and a corresponding integrated circuit layout is disclosed. The method includes identifying a voltage condition associated with a portion of the circuit schematic, and assigning a pseudo diode to the portion of the circuit schematic that is uniquely associated with the identified voltage condition. The method further includes coding a pseudo layer associated with an integrated circuit layout of the circuit schematic in accordance with content of the assigned pseudo diode, and verifying consistency between the circuit schematic and the corresponding integrated circuit layout by extracting the pseudo layer from the integrated circuit layout and comparing information of the pseudo layer to the assigned pseudo diode in the circuit schematic.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.