Three-dimensional integrated circuits and techniques for fabrication thereof
US7897428B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 3, 2008 |
| Grant date | Mar 1, 2011 |
| Priority date | — |
| Expiry date | Jul 5, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/9212
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Integrated circuits having complementary metal-oxide semiconductor (CMOS) and photonics circuitry and techniques for three-dimensional integration thereof are provided. In one aspect, a three-dimensional integrated circuit comprises a bottom device layer and a top device layer. The bottom device layer comprises a substrate; a digital CMOS circuitry layer adjacent to the substrate; and a first bonding oxide layer adjacent to a side of the digital CMOS circuitry layer opposite the substrate. The top device layer comprises an analog CMOS and photonics circuitry layer formed in a silicon-on-insulator (SOI) layer having a buried oxide (BOX) with a thickness of greater than or equal to about 0.5 micrometers; and a second bonding oxide layer adjacent to the analog CMOS and photonics circuitry layer. The bottom device layer is bonded to the top device layer by an oxide-to-oxide bond between the first bonding oxide layer and the second bonding oxide layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.