Method of fabricating a field-effect transistor having robust sidewall spacers
US7897501B2 · kind B2 · utility
6Cited by
9References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 14, 2008 |
| Grant date | Mar 1, 2011 |
| Priority date | — |
| Expiry date | Jan 14, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0212
Abstract
A method of fabricating a semiconductor device is disclosed. The method of fabricating a semiconductor device provides a semiconductor substrate; forming a gate stack overlying the semiconductor substrate; forming spacers each having a first inner spacer and a second outer spacer on sidewalls of the gate stack; forming a protective layer on sidewalls of the spacers, covering a part of the semiconductor substrate, wherein an etching selectivity of the protective layer is higher than that of the first inner spacer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.