Method of forming vertically offset bond on trace interconnects on recessed and raised bond fingers
US7897502B2 · kind B2 · utility
1Cited by
1References
26Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 10, 2008 |
| Grant date | Mar 1, 2011 |
| Priority date | — |
| Expiry date | Jan 24, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/1476
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of making a semiconductor device comprises forming a first conductive layer recessed below a surface of a substrate. The method further comprises forming a second conductive layer raised above the surface of the substrate to create a vertical offset between the first and second conductive layers. The method further comprises forming an interconnect structure on the first and second conductive layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.