Wafer-level stack package and method of fabricating the same
US7897511B2 · kind B2 · utility
2Cited by
1References
30Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 21, 2008 |
| Grant date | Mar 1, 2011 |
| Priority date | — |
| Expiry date | Mar 12, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19043
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a semiconductor device includes forming an integrated circuit region on a semiconductor wafer. A first metal layer pattern is formed over the integrated circuit region. A via hole is formed to extend through the first metal layer pattern and the integrated circuit region. A final metal layer pattern is formed over the first metal layer pattern and within the via hole. A plug is formed within the via hole. Thereafter, a passivation layer is formed to overlie the final metal layer pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.