Process for fabricating a strained channel MOSFET device
US7898028B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 23, 2007 |
| Grant date | Mar 1, 2011 |
| Priority date | — |
| Expiry date | Mar 20, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/017
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for fabricating a MOSFET device featuring a channel region comprised with a silicon-germanium component is provided. The process features employ an angled ion implantation procedure to place germanium ions in a region of a semiconductor substrate underlying a conductive gate structure. The presence of raised silicon shapes used as a diffusion source for a subsequent heavily-doped source/drain region, the presence of a conductive gate structure, and the removal of dummy insulator previously located on the conductive gate structure allow the angled implantation procedure to place germanium ions in a portion of the semiconductor substrate to be used for the MOSFET channel region. An anneal procedure results in the formation of the desired silicon-germanium component in the portion of semiconductor substrate to be used for the MOSFET channel region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.