Method and apparatus for dynamic threshold voltage control of MOS transistors in dynamic logic circuits
US7898297B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 9, 2007 |
| Grant date | Mar 1, 2011 |
| Priority date | — |
| Expiry date | Dec 29, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/854
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Metal-oxide semiconductor (MOS) transistors that are operable at voltages below 1.5V, that are area efficient, and that exhibit improved drive strength and leakage current that are disclosed. A dynamic threshold voltage control scheme is used that does not require a change to existing MOS technology processes. Threshold voltage of the transistor is controlled, such that in the Off state, the threshold voltage of the transistor is set high, keeping the transistor leakage to a small value. The advantages provided by apply to dynamic logic, as well as in the specific well separation imposed by design rules because well potential difference are lower than the supply voltage swing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.