Correction of sampling mismatch in time-interleaved analog-to-digital converters
US7898446B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 14, 2009 |
| Grant date | Mar 1, 2011 |
| Priority date | — |
| Expiry date | Aug 19, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/1215
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A time-interleaved analog-to-digital converter (ADC) is provided. The ADC generally comprises a first ADC, a second ADC, correction circuit, a divider, and a clocking circuit. The first ADC receives an analog input signal and generates a first output and a differentiated output. The second ADC receives the analog input signal and generates a second output. The correction circuit receives the first output, the second output, and the differentiated output and generates a first error signal and a second error signal. The divider receives the first error signal and the second error signal and generates a timing error by dividing the second error signal by the first error signal, and the clocking circuit receives a clock signal and the timing error and generates a plurality of corrected clocking signals, where each of the first and second ADCs receives at least one of the clocking signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.