Read operation for memory with compensation for coupling based on write-erase cycles
US7898864B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 24, 2009 |
| Grant date | Mar 1, 2011 |
| Priority date | — |
| Expiry date | Sep 23, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A read operation for non-storage elements compensates for floating gate-to-floating gate coupling and effects of program-erase cycles. During programming of a word line WLn+1, the threshold voltages of previously-programmed storage elements on WLn are increased due to coupling. To compensate for the increase, during a subsequent read operation of WLn, different sets of pass voltages are applied to WLn+1 for each control gate read voltage which is applied to WLn. The pass voltages vary in each different set so that they are a function of the control gate read voltage which is applied to WLn. The pass voltages may also be a function of a number of program-erase cycles. A higher amount of compensation is provided by increasing the pass voltages as the number of program-erase cycles increases.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.