Microprocessor having a power-saving instruction cache way predictor and instruction replacement scheme
US7899993B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 9, 2009 |
| Grant date | Mar 1, 2011 |
| Priority date | — |
| Expiry date | Apr 9, 2029 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Microprocessor having a power-saving instruction cache way predictor and instruction replacement scheme. In one embodiment, the processor includes a multi-way set associative cache, a way predictor, a policy counter, and a cache refill circuit. The policy counter provides a signal to the way predictor that determines whether the way predictor operates in a first mode or a second mode. Following a cache miss, the cache refill circuit selects a way of the cache and compares a layer number associated with a dataram field of the way to a way set layer number. The cache refill circuit writes a block of data to the field if the layer number is not equal to the way set layer number. If the layer number is equal to the way set layer number, the cache refill circuit repeats the above steps for additional ways until the block of memory is written to the cache.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.