Handling data cache misses out-of-order for asynchronous pipelines
US7900024B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 17, 2008 |
| Grant date | Mar 1, 2011 |
| Priority date | — |
| Expiry date | Apr 21, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3861
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Mechanisms for handling data cache misses out-of-order for asynchronous pipelines are provided. The mechanisms associate load tag (LTAG) identifiers with the load instructions and uses them to track the load instruction across multiple pipelines as an index into a load table data structure of a load target buffer. The load table is used to manage cache “hits” and “misses” and to aid in the recycling of data from the L2 cache. With cache misses, the LTAG indexed load table permits load data to recycle from the L2 cache in any order. When the load instruction issues and sees its corresponding entry in the load table marked as a “miss,” the effects of issuance of the load instruction are canceled and the load instruction is stored in the load table for future reissuing to the instruction pipeline when the required data is recycled.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.